1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory of a type having a redundant memory cell group serving as a sub-memory disposed in addition to a memory cell group formed into blocks disposed on a chip of the semiconductor as to use the redundant memory cells if a portion of the common memory cells has encountered a defect.
2. Related Background Art
Hitherto, a semiconductor memory, and more particularly, a MOS memory has been used recently as a large scale and ultra high speed memory. Although an attempt has been made to raise the degree of integration of a semiconductor memory by employing MOS memory, a defect occurring in the process of manufacturing the MOS memories arises a problem of deterioration in the manufacturing yield. That is, even if one memory cell among a plurality of memory cells has a problem during a process of manufacturing highly integrated MOS memories, the overall advantage of the memory cells is lost, causing the yield to deteriorate when the memory capacity is intended to be enlarged.
In order to improve the manufacturing yield of the memories, technology has been suggested which comprises sub-memory cells previously disposed on the chip in addition to a common memory cell group as to be used if a problem takes place among the common memory cells.
If a semiconductor memory having a total storage capacity of 16 megabits is constituted for example, a process is employed which comprises the steps of: a plurality of memory cells are divided into 8 memory blocks before they are disposed; each memory block is divided into 16 memory mats; each memory mat is divided into 8 unit arrays for replacing; each memory mat is constituted by a plurality of memory cell columns commonly having a division word line; and a redundant row array and a redundant column array are disposed in each 2 megabit memory block, wherein each unit array for replacing is replaced by the redundant column array if any one of data lines of a memory mat in each memory block has encountered a problem.
Structures relating to the foregoing technology are exemplified by disclosures filed in Japanese Patent Laid-Open No. 59-135700, Japanese Patent Laid-Open No. 3-105799, Japanese Patent Laid-Open No. 3-15078, Japanese Patent Laid-Open No. 3-1627995, Japanese Patent Laid-Open No. 2-208897 and U.S. patent Ser. No. 4,473,895.
However, the foregoing conventional technology sometimes encounters a problem in that, if defects of data lines or the like have concentrically taken place in one block, the number of redundant columns of the redundant memory cell array becomes short, and accordingly replacement cannot be performed. If three unit arrays for replacing of the memory mat has encountered defects in a case where two redundant column arrays are disposed in each block for example, two unit arrays for replacing can be replaced by the redundant column arrays. However, the residual unit array for replacing cannot be replaced.
In order to prevent the foregoing problem, it might be feasible to increase the number of redundant column arrays. However, employment of the foregoing structure causes the regions of the redundant column arrays to increase in each memory block, and therefore the area of the chip is enlarged excessively.